This invention relates generally to the field of radio frequency (RF) communications, and, more specifically, to an improved technique for recovering the clock signal from a stream of digital data received by a mobile radio. The invention is particularly useful for mobile radios operating in a time division multiplexed (TDM) digital communication system having Gaussian Minimum Shift Keying (GMSK) modulation.
Recently, there has been an increased demand for digital voice, digitally-encrypted voice, and high-speed data communications over land mobile radio channels. Since the radio frequency spectrum is inherently limited, one must devise new system concepts and organizational features to accommodate the increased demand for mobile and portable radio communication services. Time-division multiple access (TDMA) is one method of achieving more efficient spectrum utilization.
In its simplest form, a TDMA system is comprised of a transmitting base station capable of time-multiplexing messages from at least two users on a single RF channel, and one or more remote receiving stations capable of receiving at least one of the time-multiplexed messages. Typically, the receiving station would be a mobile or portable unit capable of transmitting a TDM message to the base station (or repeater station) on a second (or the same) RF channel. Refer to U.S. Pat. No. 4,742,514, entitled "Method and Apparatus for Controlling a TDM Communications Device", for further information regarding TDMA.
In a TDM system, like most digital communication systems, it is necessary to establish a clock rate in the receiving station that is continuously synchronized with the clock rate of the transmitting station in order to precisely recover the digital data. Continuous bit synchronization, as used herein, means that the number of bits into the transmission channel is equal to the number of bits recovered from the channel over a given time period. This requirement means that the frequency and phase of the receive clock signal must accurately track that of the transmit clock.
Bit synchronization over an RF transmission path is very difficult to maintain, primarily due to Rayleigh fading. Any method of continuous bit synchronization must withstand RF phase jumps, channel fading, drift between mobile and base station clocks, and bit slippage due to an out of lock phase-locked loop (PLL) at the mobile or base site. Moreover, the clock recovery mechanism must be sufficiently tolerant of noise such that it does not readily loose synchronization with the digital signal in the presence of random noise pulses.
An additional requirement of a clock recovery circuit for a simplex transceiver is that it maintain bit synchronization when no data message is being received, i.e., during the transmit time slot of a TDM system. Another very important requirement of a clock recovery circuit for a remote unit in a TDM system is that it should update the recovered clock phase information utilizing data from the other TDM channels when the remote is transmitting. However, in many applications, this synchronization information may not be obtained from the synchronization (sync) word in the unused time slot, since the radio may not be able to change channels quickly enough to receive the sync word.
Hence, the ideal TDM mobile clock recovery circuit would have fast acquisition of the transmitted data message clock rate, update the clock phase information utilizing random data, and maintain synchronization during the mobile transmit time slot as well as through periods of signal fading.
Various methods have been used in the past to achieve synchronization of the mobile and base station clocks. One approach is to send the clock signal along with the data, while another approach is to encode the clock into each digit such that the message carries its own synchronizing information. These techniques are undesirable in RF communication systems, since the additional clock information requires either a wider bandwidth or a reduced data rate.
U.S. Pat. No. 4,592,076, entitled "Synchronizing Signal Recovery Circuit for Radio Telephones", utilizes a digital phase-locked loop to recover the clock rate in response to an appropriate bit rate timing signal derived from the data signal bit stream. This patent, however, assumes the data signal information is present at all times, which is not a valid assumption in a TDM system. Furthermore, the circuit would lose synchronization in periods of noisy or faded signals. Still further, in using a single PLL, the initial transmit-to-receive transient produced by the radio's frequency synthesizer may direct the clock recovery PLL away from the desired frequency, thus producing additional time when the receive clock is not synchronized with the transmit clock.
Another technique for clock recovery, described in U.S. Pat. No. 4,400,817 entitled "Method and Means of Clock Recovery in a Received Stream of Digital Data", utilizes a programmable divider coupled to a reference clock signal. The recovered clock signal is compared to the received data signal, and the divider is programmably altered to shift the phase of the recovered clock. Again, this phase comparison technique utilizing a zero-crossing detector which would not maintain synchronization during the transmit burst of a TDM mobile transceiver.
A need, therefore, exists to provide a method and means for clock recovery from a stream of digital data which provides continuous bit synchronization during periods when the mobile transceiver is transmitting, and also during fading periods when the received signal drops below receiver sensitivity.